1995,1999 data sheet compound transistor m pa102 features ? two built-in differential amplifier circuits: (each transistor has f t 9 ghz) ? outstanding h fe linearity ? two package options: m pa102b: superior thermal dissipation due to studded 14-pin ceramic package m pa102g: reduced circuit size due to 14-pin plastic sop package for surface mounting description and applications the m pa102 is a user configurable silicon bipolar transistor array consisting of two separate differential amplifiers. it is available in a surface mount (14-pin plastic sop) package and a 14-pin ceramic package. typical applications include: pulse pattern generators, oscillators, differential amps, high speed comparators, electro-optic signal processing up to 1 gigabits/second, and advanced cellular phone systems. ordering information part number package m pa102b-e1 14-pin ceramic package m pa102g-e1 14-pin plastic sop (225 mil) absolute maximum ratings (t a = +25 c) symbols parameters units ratings v cbo * collector to base voltage v 15 v ceo * collector to emitter voltage v 6 v ebo * emitter to base voltage v 2.5 i c * collector current ma 40 p t power dissipation m pa102b mw 650 m pa102g mw 350 t j junction temperature m pa102b c 200 m pa102g c 125 t stg storage temperature m pa102b c C55 to +200 m pa102g c C55 to +125 * absolute maximum ratings for each transistor. high frequency npn transistor array caution electro-static sensitive devices document no. p10707ej2v0ds00 (2nd edition) date published october 1999 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. the mark shows major revised points.
m pa102 2 data sheet p10707ej2v0ds00 package dimensions (unit: mm) m pa102b 14 pin ceramic package f 0.8 top view 0.35 1.27 6.2 5.0 max. 4.5 min. 0.08 2.3 min. 1.6 f 2. 7 max. side view bottom view 1.8 3.0 m pa102g 14 pin plastic sop (225 mil) 10.2 0.26 1.27 0.10 note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. detail of lead end m 17 14 8 1.42 max 6.55 0.2 4.38 0.1 0.6 0.2 1.1 0.16 0.10 0.15 +0.10 ?.05 3 +7 ? 0.40 +0.10 ?.05 1.49 0.1 0.1 1.59 +0.21 ?.20 see connection diagram for description of leads.
m pa102 3 data sheet p10707ej2v0ds00 electrical characteristics (unless otherwise specified t a = +25 c m pa102b, m pa102g common) symbols parameters and conditions units min. typ. max. i cbo collector cutoff current at v cb = 5 v, i e = 0 (q1, q2, q4, q5) m a 1.0 i ebo emitter cutoff current at v eb = 1 v, i c = 0 (q3, q6) m a 1.0 h fe direct current amplification at v ce = 3 v, i c = 1 ma (q3, q6) 40 100 250 h fe1 /h fe2 direct current amplification ratio at v ce = 3 v, i c = 1 ma, (q3, q6) 0.9 1.0 1.1 c cb collector to base capacitance at v cb = 3 v, f = 1 mhz (q1, q2, q4, q5) pf 0.9 1.8 c eb emitter to base capacitance at v eb = 0, f = 1 mhz (q3, q6) pf 1.4 2.8 c cs collector/substrate capacitance at v cs = 3 v, f = 1 mhz (q1, q2, q4, q5) pf 1.4 2.8 f t gain bandwidth product * at v ce = 3 v, i c = 10 ma ghz 9.0 * measured by installing a single transistor in a micro-x package: the value shown is a reference value. connection diagram (top view) m pa102b m pa102g sub sub 14 13 12 11 10 9 8 1234567 q 1 q 2 q 3 q 4 q 5 q 6 test circuit schematic* (for electrical characteristics measurements excluding f t ) q 1 q 2 1 4 13 14 q 3 2 3 * see performance characteristics for voltage. q 1 q 2 q 3 14 13 12 11 10 9 8 1234567 sub sub q 6 q 4 q 5
m pa102 4 data sheet p10707ej2v0ds00 typical performance characteristics (t a = +25 c) 10 8 6 4 2 0 012345 pin 1 to pin 3 voltage, v i b = 20 a m 40 60 80 100 collector current vs. pin 1 to pin 3 voltage 20 0.4 collector current, i c (ma) base to emitter voltage, v be (v) collector current vs. base to emitter voltage collector current, i c (ma) 10 2 5 1 0.1 0.2 0.5 0.5 0.6 0.7 0.8 0.9 1.0 v ce = 3 v 1000 0.5 1 2 collector current, i c (ma) dc current gain vs. collector current 12 10 8 6 4 1 gain bandwidth product, f t (ghz) collector current, i c (ma) gain bandwidth product vs. collector current dc current gain, h fe 200 500 100 20 50 10 51020 50 v ce = 3 v 50 2 5 10 20 v ce = 5 v 3 v 1 v 100 50 18 14 10 6 2 .01 frequency, f (ghz) 20 10 0 1 gain (db) collector current, i c (ma) gain and noise figure of individual transistor power gain (db) i cc = 20 ma i cc = 10 ma i cc = 5 ma power gain vs. frequency 2.0 .02 .05 .1 .2 .5 1.0 2 5 10 20 50 100 v cc = 3 v f = 1 ghz 8 6 4 2 0 noise figure, nf (db) gain nf 0 1.1
m pa102 5 data sheet p10707ej2v0ds00 notes on correct use (1) observe precautions for handling because of electro-static sensitive devices. (2) form a ground pattern as wide as possible to minimize ground impedance (to prevent undesired operation). (3) design circuits connected sub pin to the lowest voltage to prevent latch-up. (4) design circuits as each pin voltage difference within 15 v maximum. recommended soldering conditions this product should be soldered in the following recommended conditions. other soldering methods and conditions than the recommended conditions are to be consulted with our sales representatives. m pa102g soldering process soldering conditions recommended condition symbol infrared ray reflow package peak temperature: 235 c, hour: within 30 s. (more than 210 c), time: 2 times, limited days: no. note vps package peak temperature: 215 c, hour: within 40 s. (more than 200 c), time: 2 times, limited days: no. note wave soldering soldering tub temperature: less than 260 c, hour: within 10 s. time: 1 time, limited days: no. note pin part heating pin area temperature: less than 300 c, hour: within 3 s./pin limited days: no. note m pa102b soldering process soldering conditions symbol infrared ray reflow peak packages surface temperature: 230 c or below, reflow time: 10 seconds or below (210 c or higher), number of reflow process: 1, exposure limit * : none partial heating method terminal temperature: 260 c or below, flow time: 10 seconds or below, exposure limit * : none note it is the storage days after opening a dry pack, the storage conditions are 25 ?c, less than 65 % rh. caution the combined use of soldering method is to be avoided (however, except the pin area heating method). for details of recommended soldering conditions for surface mounting, refer to information document semiconductor device mounting technology manual (c10535e). ir35-00-2 vp15-00-2 ws60-00-1
m pa102 6 data sheet p10707ej2v0ds00 [memo]
m pa102 7 data sheet p10707ej2v0ds00 [memo]
m pa102 nesat (nec silicon advanced technology) is a trademark of nec corporation. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8
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